The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

1. Nilesh Kamdar addressed simulation, interoperability testing, and managing chiplet data in his presentation. Artificial intelligence (AI) has become central to EDA design optimization and debugging ...

Siemens plans to integrate Aster's advanced "shift-left" design for test functionality into Siemens' Xpedition and Valor ...

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Vivek Yadav, an engineering manager from ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

Getting an integrated circuit (IC) from design to test is an arduous process that encompasses a number of steps, including: This is an iterative process and can take months, so every step should be ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...