Semiconductor Engineering

IEEE 1076.4-VHDL Synthesis Package – Floating Point

The goal of VITAL (VHDL Initiative Towards ASIC Libraries) was to accelerate the development of sign-off quality ASIC macro-cell simulation libraries written in VHDL by leveraging existing ...
Semiconductor Engineering

IEEE 1076.1.1-VHDL-AMS Standard Packages

Work started on the multiple energy domain packages in 2001 with the IEEE group being officially formed in May 2002. The committee approved it in 2004 and created an updated version in 2011. This ...
Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...
Hackaday

Did You Know YoSys Knows VHDL Too?

We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in ...