Design-Reuse

SoC Test and Verification -> ATE struggles to keep pace with VLSI

The cost of testing complex system-on-chip designs will soon surpass the cost of manufacturing them. Clearly this is an unstable situation. It is simply too hard to keep up with Moore's Law. While the ...
EDN

Weak memory market impacts test probe card market, VLSI Research says

Weakness in the semiconductor industry pushed sales of IC wafer testing probe cards down to half of the five-year historic average, or 13.9%, in 2007 according to Santa Clara, Calif.-based market ...
Design-Reuse

Importance of VLSI Design Verification and its Methodologies

In the dynamic world of VLSI (Very Large-Scale Integration), the demand for innovative products is higher than ever. The journey from a concept to a fully functional product involves many challenges ...
EDN

A semiconductor test primer (complete book review)

Return to original Test Digest book review. VLSI Test Principles and Architectures: Design for Testability, Laung-Terng Wang, Chen-Wen Wu, and Xiaoquing Wen (editors), Elsevier Science ...
UMass Lowell

Electrical and Computer Engineering

This link below contains information about the Cadence design tools used extensively in classes in the Electrical and Computer Engineering Department at UMass Lowell. Students obtain practical ...