When it comes to test portability between simulation, emulation and silicon, it may be time to consider a higher level of abstraction using graph-based technology. Is it time to move up again? When it ...

In New test points slash ATPG test pattern count, I described a new type of test point technology used with scan compression for device testing. The key benefit of using test points with embedded ...

Why are test points a crucial element in developing a successful circuit? Types of test points available, and the different techniques that employ them. Electronic design has always been an endeavor ...

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...

Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...

The exponential growth in design sizes has rendered the traditional methods of design-for-test, layout, and timing closure no longer sufficient. Design and test engineers not only have to constantly ...