EDN

Translator bridges Vera code to SystemVerilog 3.1

Santa Cruz, Calif. – Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments ...
Design-Reuse

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis ...
Electronic Design

Getting To A Higher Level

Meanwhile, SystemVerilog offers a direct programming interface (DPI) to SystemC, which means that SystemVerilog code can directly call functions written in C, C++, or SystemC without resorting to the ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
EDN

Translator ties Vera code to SystemVerilog 3.1

SANTA CRUZ, Calif. — Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments ...