A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves ...

Part 1 shows how to increase performance through code partitioning, function inlining, and other techniques. Part 3 shows how to optimize code by modifying the placement of functions in memory. The ...

Editor's Note: This is part 2 of a four-part series. In part 1, we showed how to do efficient 4×4 complex matrix inversion on the StarCore SC3850. The newly released Freescale SC3850 StarCore DSP ...

We have described and applied a technique for selection of processor cache configurations for low power using a parameter defined as a product of the cache miss rate and cache size. 1. Introduction ...

In the semiconductor world, integration is omnipresent, driven by Moore’s Law. Integration reduces power and cost while increasing performance. The latest realization of this trend is the ...

When talking about CPU specifications, in addition to clock speed and number of cores/threads, ' CPU cache memory ' is sometimes mentioned. Developer Gabriel G. Cunha explains what this CPU cache ...

IBM’s Tuesday, October 15th announcement of the PowerPC 970 was one of the most heavily anticipated processor announcements in recent memory. Mac users, would-be Mac users, Linux enthusiasts, and ...

We have a little more than a week to wait for Intel to release the new Core 2 range of CPUs. These are based on a new processor architecture, which, instead of just pumping up the CPU’s frequency, ...

System-on-a-Chip (SoC) designers have a problem, a big problem in fact, Random Access Memory (RAM) is slow, too slow, it just can’t keep up. So they came up with a workaround and it is called cache ...