EDN

Designing DDR3 SDRAM controllers with today’s FPGAs

The recently introduced DDR3 SDRAM technology paves the way to higher data rates (from 800 Mbps to 1600 Mbps) and provides higher performance for many systems that depend on data, video, or packet ...
EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
Design-Reuse

Lattice Announces Immediate Availability of DDR SDRAM Controller IP Core for LatticeECP and LatticeEC FPGA Families

Pipelined Intellectual Property Core Validated In-System At 200MHz/400DDR; Designed For High-Speed Operation Using Embedded DDR Support In LatticeECP/LatticeEC FPGA Devices The Double Data Rate (DDR) ...
Design-Reuse

DDR SDRAM Controller IP Designed for Reuse

This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. The development of integrated systems-on-a-chip (SoC) is based ...
Electronic Design

AKA Packages FPGA With Processors

Advanced Knowledge Associates (AKA) was showing off its Prepackaged Reconfigurable Integrated System-on-Module (PRISM) line including the PRISM 150, 200, and 300 (Fig. 1). These aggregate discrete ...
Electronic Design

IP Core Accelerates FPGA Access To DDR2 SDRAM

The company has announced what it is calling the industry’s first 533-Mb/s DDR2 SDRAM controller IP core supporting the LatticeECP2/ECP2M low-cost FPGA families, and the high-end LatticeSC FPGA family ...