Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

Computer architecture researchers evaluate key areas such as pipelining, organization, instruction issue, branching, and exception handling when considering asynchronous and synchronous design and ...

Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s ...

Non-mainstream technologies can offer advantages over more commonly used approaches, but usually at some additional cost (otherwise they’d probably be mainstream). The additional cost could be in ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

“We’re replacing dictatorship with anarchy!” Karl Fant tells me emphatically. Ponytailed and animated, the founder and chief technical officer of Theseus Logic fills the whiteboard with sweeping ...

Micropipelines. Ivan E. Sutherland: The Turing Award Lecture. Communications of the ACM, Vol. 32, No. 6, pages 720¿738; June 1989. Asynchronous Circuits and Systems. Special issue of Proceedings of ...