Semiconductor Engineering

HBM-Enabled FPGA-Based Graph Processing Accelerator

A technical paper titled “ACTS: A Near-Memory FPGA Graph Processing Framework” was published by researchers at University of Virginia and Samsung. “Despite the high off-chip bandwidth and on-chip ...
Nasdaq

MoSys Announces Availability of its Graph Memory Engine (GME) Accelerator IP Targeting Packet Classification on Intel's Stratix 10 FPGAs

SAN JOSE, CA / ACCESSWIRE / June 8, 2020 / MoSys, Inc. (NASDAQ:MOSY), a provider of semiconductor solutions that enable fast, intelligent data access for Cloud, networking, security and communications ...
Electronic Design

An FPGA-Based Solution for a Graph Neural Network Accelerator

Graph Neural Networks (GNN) drive high demand for compute and memory performance. Software-only based GNN algorithm processing is insufficient to run these workloads. Learn how FPGA-based hardware ...
Electronic Design

MoSys’ Graph Memory Engine Accelerator IP Targets Packet Classification on Intel’s Stratix 10 FPGAs

The GME product offering includes software, firmware and RTL and utilizes a common API and common RTL interface to facilitate platform portability. MoSys announced that its Graph Memory Engine (GME) ...